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APL5312
Ultra-Low-Noise, High PSRR, Low-Dropout, 300mA Linear Regulator
Features
* * * * * * * * * * * * *
Wide Operating Voltage: 2.3V~6V Low Dropout Voltage: 290mV @ 3V/300mA Fixed Output Voltages: 1.5V~3.5V with Step 100mV, 2.85V Guaranteed 300mA Output Current High PSRR: 74dB before 10kHz Low Output Noise: 36VRMS at 100Hz to 100kHz Current-Limit Protection Controlled Short Circuit Current: 50mA Over-Temperature Protection Stable with 1F Capacitor for Any Load Excellent Load/Line Transient SOT-23-5 and SC-70-5 Packages Lead Free and Green Devices Available (RoHS Compliant)
General Description
The APL5312 is an ultra low noise, low dropout linear regulator, which operates from 2.3V to 6V input voltage and delivers up to 300mA. Typical dropout voltage is only 290mV at 300mA loading. Designed for use in RF applications, the high PSRR 74dB and low noise 36VRMS makes it an ideal choice. Design with an internal P-channel MOSET pass element, the APL5312 maintains a low supply current, independent of the load current and dropout voltage. Other features include thermal-shutdown protection and currentlimit protection to ensure specified output current and controlled short-circuit current. The APL5312 regulator comes in a miniature SOT-23-5 and SC-70-5 package.
Pin Configuration
SOT-23-5/SC-70-5
Applications
* * * *
Cellular Phones Portable and Battery-Powered Equipment Wireless LANs GPS
VIN GND SHDN
1 2 3
5
VOUT
4
BP
APL5312
Ordering and Marking Information
APL5312 Assembly Material Handling Code Temperature Range Package Code Voltage Code Package Code B : SOT-23-5 S5 : SC-70-5 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Voltage Code 15 : 1.5V 30 : 3.0V Assembly Material G : Halogen and Lead Free Device
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for MSL classification at lead-free peak reflow temperature. ANPEC defines "Green" to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Jun., 2009 1 www.anpec.com.tw
APL5312
Ordering and Marking Information (Cont.)
SOT-23-5 packages
Product Name Marking APL5312-15B APL5312-19B APL5312-23B APL5312-27B APL5312-31B APL5312-35B
SC-70-5 packages
Product Name APL5312-15S5 APL5312-19S5 APL5312-23S5 APL5312-27S5 APL5312-31S5 APL5312-35S5 Marking 339 33D 33H 33L 33P 33T
Product Name APL5312-16B APL5312-20B APL5312-24B APL5312-28B APL5312-32B APL5312-285B
Marking 33AX 33EX 33IX 33MX 33QX 33dX
Product Name Marking APL5312-17B APL5312-21B APL5312-25B APL5312-29B APL5312-33B 33BX 33FX 33JX 33NX 33RX
Product Name APL5312-18B APL5312-22B APL5312-26B APL5312-30B APL5312-34B
Marking 33CX 33GX 33KX 33OX 33SX
339X 33DX 33HX 33LX 33PX 33TX
Product Name APL5312-16S5 APL5312-20S5 APL5312-24S5 APL5312-28S5 APL5312-32S5 APL5312-285S5
Marking 33A 33E 33I 33M 33Q 33d
Product Name APL5312-17S5 APL5312-21S5 APL5312-25S5 APL5312-29S5 APL5312-33S5
Marking 33B 33F 33J 33N 33R
Product Name APL5312-18S5 APL5312-22S5 APL5312-26S5 APL5312-30S5 APL5312-34S5
Marking 33C 33G 33K 33O 33S
Absolute Maximum Ratings
Symbol VIN, VOUT SHDN/BP TJ TSTG TSDR Input Voltage or Out Voltage
(Note 1)
Rating 6.5 6.5 0 to 125 -65 to +150 260 Unit V V X C X C X C
Parameter
VOUT Shutdown Control Pin/Bypass Signal Pin Operating Junction Temperature Storage Temperature Range Maximum Lead Temperature Soldering, 10 Seconds
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Thermal Characteristics
Symbol JA Parameter Thermal Resistance-Junction to Ambient
(Note 2)
Rating SOT-23-5 SC-70-5 240 325 410 310
Unit
o
C/W
Power Dissipation, TA = 25 oC (Note 3) PD SOT-23-5 SC-70-5 mW
Note 2 : JA is measured with the component mounted on a high effective thermal conductivity test board in free air. Note 3 : When mounted on a (Copper foil area 50%, 45x45x1.6tmm) glass epoxy board.
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Jun., 2009
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APL5312
Electrical Characteristics
Unless otherwise noted these specifications apply over full temperature, VIN = VOUT+1V, CIN = COUT = 1 F, TA = -40 to 85C. Typical values refer to TA = 25C.
Symbol VIN VOUT Parameter Input Voltage Output Voltage Accuracy Output Voltage Range ILIMIT IQ IOUT REGLINE REGLOAD Circuit Current Limit Quiescent Current Load Current Line Regulation Load Regulation Dropout Voltage (Note 4) VOUT+0.5VTC COUT
Note 4 : Dropout voltage definition: VIN-VOUT when VOUT is 2% below the value of VOUT for VIN= VOUT +1V.
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Jun., 2009
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APL5312
Typical Operating Characteristics
Quiescent Current vs. Ambient Temperature
125
Quiescent Current vs. Output Current
180 160 Quiescent Current (A) 140 120
Quiescent Current (A)
120
115
VIN=5.5V VIN=4.5V
110
100 80 60
105
100 -40 -15 10 35 60 85
0
50
Ambient Temperature (C)
100 150 200 Output Current (mA)
250
300
Quiescent Current vs. Input Voltage 200 180 160
Quiescent Current (A) 400 350 Droput Voltage (mv) 300 250 200 150 100 50 0
Dropout Voltage vs.Output Current
VOUT=2.5V
140 120 100 80 60 40 20 0 0 1 2 3 4 5 6
Input Voltage (V)
TA=85 oC TA=25 oC
0
50
100
150
200
250
300
Output Current (mA)
Dropout Voltage vs. Output Current
600 500 Shutdown Exit Delay (s) Dropout Voltage (mV) 400 300 200 100 0 0
Shutdown Exit Delay
140 120 100 80 60 40 20 0 1.5
VOUT=1.5V
CBP=10nF
VOUT=2.2V VOUT=3.3V
50
100 150 200 Output Current (mA)
250
300
1.8
2.1 2.4 2.7 Output Voltage (V)
3
3.3
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Jun., 2009
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APL5312
Typical Operating Characteristics (Cont.)
PSRR vs. Frequency
560
-20 -30 -40 IOUT=10mA
Current Limit vs. Input Voltage
540 520
Current Limit (mA)
TA=25oC
PSRR (dB)
-50 -60 -70 -80 -90 -100 -110 20 100 1k 10k 100k 200k
500 480 460 440 420 400 4 4.5 5
Input Voltage (V)
TA=85oC
VIN=5V
VIN=4.5V
5.5
6
Frequency (Hz)
Output Noise vs. BP Capacitance
160 140
Output Noise (VRMS) Maximum Power Dissipation (mW)
450 400 350 300 250 200 150 100 50 0 0
Maximun Power Dissipation vs. Ambient Temperature
SOT-23-5
120 100 80 60 40 20 0 1
IOUT=10mA IOUT=100mA
SC-70-5
10
BP Capacitance (nF)
100
25
50
75
100
125
Ambient Temperature (C)
100
Region of Stable COUT ESR vs. Load Current
VOUT=2.5V CIN=COUT=1F, Y5V
10 COUT ESR ()
Instable
1
0.1
Stable
0.01 0 50
Instable
100 150 200 Output Current (mA)
250
300
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APL5312
Typical Operating Characteristics (Cont.)
Load Transient
Line Transient
VOUT(50mV/div) V (50mV/div)
OUT
VIN=4.5V~5.5V VIN=4.5V~5.5V
IIOUT(1~300mA) OUT (1~300mA) Tr=1s T r=1s
(50mV/div) VOUT(50mV/div) OUT IIOUT=10mA =10mA OUT
Time (0.1ms/div)
Time (0.1ms/div)
Exiting Shutdown Waveform
Entering Shutdown Delay
I OUT =100mA IOUT=100mA C BP=10nF CBP =10nF SHDN (1V/div)
IIOUT=100mA OUT =100mA CBP=10nF CBP=10nF
SHDN (1V/div)
VOUT (1V/div)
VOUT (1V/div)
Time (50s/div)
Time (0.1ms/div)
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Jun., 2009
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APL5312
Pin Description
PIN NO. 1 2 3 4 5 NAME VIN GND SHDN BP VOUT I I O I Voltage supply input pin GND pin Shutdown control pin, low = off, high = normal Bypass signal pin in fixed output type device Regulator output pin I/O FUNCTION
Block Diagram
VIN Thermal Shutdown & Current Limit
SHDN
Shutdown
BP
VREF
_ MOS Driver + VOUT
GND
Typical Application Circuit
VIN SHDN CIN 1F APL5312 GND
VOUT BP COUT 1F
CBP 10nF
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Jun., 2009
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APL5312
Application Information
Output Voltage Selection The APL5312 are supplied with factory-set output voltages from 1.5V to 3.5V. Capacitor Selection and Regulation Stability Input-Output (Dropout) Voltage The APL5312 uses at least a 1F capacitor on the input. This capacitor can use Aluminum, Tantalum, or Ceramic capacitors. Input capacitor with large value and low ESR provides better PSRR and line-transient response. The output capacitor also can use Aluminum, Tantalum, or Ceramic capacitor, and its proper values is at least 1F, ESR must be above 25m. Large output capacitor values can reduce noise and improve load-transient response, stability, and PSRR. W ith X5R and Y5V dielectrics, 1F is sufficient at all operating temperatures. The selection of output capacitor' is important because s it with COUT form a zero to provide the sufficient phase margin (see the Figure COUT ESR vs. Load Current). Bypass Capacitor Use a 10nF bypass capacitor at BP for low-output voltage noise. The leakage current going into the BP pin should be less than 10nA. Increasing the capacitance slightly decreases the output noise. Value above 0.1F and below 1nF are not recommended (see the Figure Output Noise vs. BP Capacitance). Noise, PSRR, and Load-Transient Response The APL5312 is designed to deliver ultra-low noise and high PSRR, as well as low dropout and low quiescent currents in battery-powered systems. When operating from sources other than batteries, improve PSRR and transient response can be achieved by increasing input and output capacitors, and bypass capacitor to form the passive filtering techniques (see Output Noise vs. BP Capacitance). Shutdown The APL5312 has an active high enable function. Force SHDN high (>1.6V) enables the VOUT, SHDN low (<0.4V) disables the VOUT. Enter the shutdown mode, it also causes the output voltage to discharge through a 500 resistance to ground. In shutdown mode, the quiescent curCopyright (c) ANPEC Electronics Corp. Rev. A.4 - Jun., 2009 8
rent can reduce to 0.1A. The SHDN pin cannot be floating, a floating SHDN pin may cause an indeterminate state on the output. If it is no use, connect to VIN for normal operation.
The minimum input-output voltage differential (dropout) determines the lowest usable supply voltage. The dropout voltage is a function of drain-to-source on resistance multiplied by the load current. Current Limit APL5312 includes a current-limit circuitry for linear regulator. The current-limit protection, which senses the current flowing to the P-channel MOSFET, and controls the output voltage. The point where limiting occurs is IOUT =500mA. The output can be shortened to the ground for an indefinite amount of time without damaging to the part. Thermal Protection Thermal protection limits total power dissipation in the APL5312. When the junction temperature exceeds +160C, the thermal sensor generates a logic signal to turn off the pass element and let IC to cool. When the IC' s junction temperature cools down by 20C, the thermal sensor will turn the pass element on again, resulting in a pulsed output during continuous thermal protection. Thermal protection is designed to protect the IC in the event of fault conditions. Operating Region and Power Dissipation The thermal resistance of the case and circuit board, ambient and junction air temperature, and the rate of air flow all control the APL5312' maximum power s dissipation. The power dissipation across the device is P = IOUT (VIN-VOUT). The maximum power dissipation is: PMAX = (TJ - TA) / (JC + CA ) JA = JC + CA where TJ - TA is the temperature difference between the junction and ambient air. JC is the thermal resistance of the package, CA is the thermal resistance through the printed circuit board, copper traces, and other materials to the surrounding air, JA
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APL5312
Application Information (Cont.)
Operating Region and Power Dissipation (Cont.) is the thermal resistance between Junction and ambient air. For continual operation, do not exceed the absolute maximum junction Temperature rating of TJ = 125C. For example: The SOT-23-5 package has maximum power dissipation 300mW at TA= 55C, relatively 225mW at SC-70-5 package (see Maximum Power Dissipation vs. Ambient Temperature). VIN = 5V, IOUT = 250mA, VOUT = 3.3V, PD = (5-3.3)V x 150mA = 255mW According the power dissipation issue, we should adapt the SOT-23-5 package. It could reduce the thermal resistance to maintain the IC longer life. The GND pin provides an electrical connection to the ground and channeling heat away. The printed circuit board (PCB) forms a heat sink and dissipates most of the heat into ambient air. Recommended Minimum Footprint
SOT-23-5
0.076
SC-70-5
0.052
0.081
0.1
0.038
0.02 Unit : Inch
0.026
0.016 Unit : Inch
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Jun., 2009
0.046
0.05
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APL5312
Package Information
SOT-23-5
D e
SEE VIEW A E1 b e1 E
c
0.25 GAUGE PLANE SEATING PLANE VIEW A
0
A2 A1
A
L
S Y M B O L A A1 A2 b c D E E1 e e1 L 0
SOT-23-5 MILLIMETERS MIN. MAX. 1.45 0.00 0.90 0.30 0.08 2.70 2.60 1.40 0.95 BSC 1.90 BSC 0.30 0 0.60 8 0.012 0 0.15 1.30 0.50 0.22 3.10 3.00 1.80 0.000 0.035 0.012 0.003 0.106 0.102 0.055 0.037 BSC 0.075 BSC 0.024 8 MIN. INCHES MAX. 0.057 0.006 0.051 0.020 0.009 0.122 0.118 0.071
Note : 1. Follow JEDEC TO-178 AA. 2. Dimension D and E1 do not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 10 mil per side.
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APL5312
Package Information
SC-70-5
D e
SEE VIEW A E1 E
b e1
c
0.15 GAUGE PLANE SEATING PLANE L VIEW A SC-70-5 INCHES MIN. 0.031 0.000 0.031 0.006 0.003 0.075 0.079 0.045 0.026 BSC 0.051 BSC MAX. 0.043 0.004 0.040 0.012 0.010 0.087 0.095 0.053 0.006 0o 0.018 8o 8o
A2 S Y M B O L A A1 A2 b c D E E1 e e1 L 0 0.15 0o MILLIMETERS MIN. 0.80 0.00 0.80 0.15 0.08 1.90 2.00 1.15 0.65 BSC 1.30 BSC A1
1.10 0.10 1.00 0.30 0.25 2.20 2.40 1.35
Note : 1. Followed from JEDEC MO-223 AB. 2. Dimension D and E1 do not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side.
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Jun., 2009
A MAX. 0.45
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APL5312
Carrier Tape & Reel Dimensions
OD0 P0 P2 P1 A E1 F K0 B SECTION A-A T B0 A0 OD1 B A SECTION B-B
d
Application
A 178.0O .00 2
H 50 MIN. P1 4.0O .10 0 H 50 MIN. P1 4.0O .10 0
H A
T1
T1 8.4+2.00 -0.00 P2 2.0O .05 0 T1 8.4+2.00 -0.00 P2 2.0O .05 0
C 13.0+0.50 -0.20 D0 1.5+0.10 -0.00 C 13.0+0.50 -0.20 D0 1.5+0.10 -0.00
d 1.5 MIN. D1 1.0 MIN. d 1.5 MIN. D1 1.00 MIN.
D 20.2 MIN. T 0.6+0.00 -0.40 D 20.2 MIN. T 0.6+0.00 -0.40
W 8.0O .30 0 A0 3.20O .20 0 W 8.0O .30 0 A0 2.40O .20 0
W
E1 1.75O .10 0 B0 3.10O .20 0 E1 1.75O .10 0 B0 2.40O .20 0
F 3.5O .05 0 K0 1.50O .20 0 F 3.50O .05 0 K0 1.20O .20 0 (mm)
SOT-23-5
P0 4.0O .10 0
Application
A 178.0O .00 2
SC-70-5
P0 4.0O .10 0
Devices Per Unit
Package Type SOT-23-5 SC-70-5 Unit Tape & Reel Tape & Reel Quantity 3000 3000
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Jun., 2009
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APL5312
Taping Direction Information
SOT-23-5
USER DIRECTION OF FEED
SC-70-5
USER DIRECTION OF FEED
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APL5312
Classification Profile
Classification Reflow Profiles
Profile Feature Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time (tP)** within 5C of the specified classification temperature (Tc) Average ramp-down rate (Tp to Tsmax) Time 25C to peak temperature Sn-Pb Eutectic Assembly 100 C 150 C 60-120 seconds 3 C/second max. 183 C 60-150 seconds See Classification Temp in table 1 20** seconds 6 C/second max. 6 minutes max. Pb-Free Assembly 150 C 200 C 60-120 seconds 3C/second max. 217 C 60-150 seconds See Classification Temp in table 2 30** seconds 6 C/second max. 8 minutes max.
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
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APL5312
Classification Reflow Profiles (Cont.)
Table 1. SnPb Eutectic Process - Classification Temperatures (Tc) Package Thickness <2.5 mm 2.5 mm Package Thickness <1.6 mm 1.6 mm - 2.5 mm 2.5 mm Volume mm <350 260 C 260 C 250 C
3
Volume mm <350 235 C 220 C
3
Volume mm 350 220 C 220 C Volume mm 350-2000 260 C 250 C 245 C
3
3
Table 2. Pb-free Process - Classification Temperatures (Tc) Volume mm >2000 260 C 245 C 245 C
3
Reliability Test Program
Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Description 5 Sec, 245C 1000 Hrs, Bias @ 125C 168 Hrs, 100%RH, 2atm, 121C 500 Cycles, -65C~150C VHBMU2KV VMMU200V 10ms, 1trU 100mA
Customer Service
Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838
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